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Integrated Circuit Systems, Inc.
ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Two LVCMOS outputs @ 3.3V, 17 typical output impedance * Selectable crystal oscillator interface or LVCMOS single-ended input * Output frequency range: 46.66MHz - 233.33MHz * VCO range: 560MHz - 700MHz * Supports the following output frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz * RMS phase jitter @ 212.5MHz (637KHz - 10MHz): 0.83ps (typical) Typical phase noise at 212.5MHz: Offset Noise Power 100Hz ............... -91.3 dBc/Hz 1KHz .............. -114.3 dBc/Hz 10KHz .............. -120.7 dBc/Hz 100KHz .............. -120.2 dBc/Hz * Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Lead-Free package RoHS compliant
GENERAL DESCRIPTION
The ICS840002I is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The ICS840002I uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840002I is packaged in a 16-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 Inputs F_SEL1 0 0 1 1 0 F_SEL0 0 1 0 1 1 M Divider Value 24 24 24 24 24 N Divider Value 3 4 6 12 4 M/N Ratio Value 8 6 4 2 6 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25
BLOCK DIAGRAM
OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown
PIN ASSIGNMENT
2
F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT
XTAL_IN 26.5625MHz
OSC
XTAL_OUT TEST_CLK Pulldown
0
F_SEL1:0
1 Phase Detector
00 01 10 11
1
VCO
0
N /3 /4 /6 /12 (default)
ICS840002I
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
Q1
M = /24 (fixed)
MR
840002AGI
Pulldown
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Integrated Circuit Systems, Inc.
ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Input Input Input Input Input Pullup Description Frequency select pins. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 16 2 3 4 5 Name F_SEL0, F_SEL1 nXTAL_SEL TEST_CLK OE MR
6 7 8 9, 10 11 12, 13 14, 15
nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN VDDO Q1, Q0 GND
Input Power Power Input Power Output Power
Selects between the crystal or TEST_CLK inputs as the PLL reference Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Pulldown Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = Pulldown reference clock frequency/n output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Output supply pin. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance 3.3V5% 2.5V5% 14 16 Test Conditions Minimum Typical 4 8 51 51 17 21 21 25 Maximum Units pF pF k k
TABLE 3. FREQUENCY SELECT FUNCTION TABLE
Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 26.04166 F_SEL1 0 0 1 1 0 F_SEL0 0 1 0 1 1 Inputs M Divider Value N Divider Value 24 3 24 24 24 24 4 6 12 4 M/N Divider Value 8 6 4 2 6 Output Frequency (MHz) 212.5 159.375 106.25 53.125 156.25
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 100 12 5 Units V V V V mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 95 12 5 Units V V V mA mA mA
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, OR
VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage OE F_SEL0:1, nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE F_SEL0:1, nPLL_SEL, MR, nXTAL_SEL, TEST_CLK
Test Conditions VDD = 3.465V VDD = 2.625V VDD = 3.465V VDD = 2.625V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VDDO = 3.3V5% VDDO = 2.5V5% VDDO = 3.3V or 2.5V5%
Minimum Typical 2 1.7 -0.3 -0.3
Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 150
Units V V V V A A A A V V
IIH
Input High Current
IIL
Input Low Current
-150 -5 2.6 1.8 0.5
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. Test Conditions Minimum Typical 26.5625 50 7 Maximum Units MHz pF Fundamental
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.67 170 113.33 56.67 12 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 0.83 0.62 0.59 0.80 0.68 200 700 54 58 Units MHz MHz MH z MH z ps ps ps ps ps ps ps % %
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF odc
Output Rise/Fall Time Output Duty Cycle
F_SEL[1:0] 00 46 F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency Range F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.67 170 113.33 56.67 12 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 0.73 0.62 0.56 0.76 0.72 200 700 54 58 Units MHz MHz MH z MH z ps ps ps ps ps ps ps % %
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF
Output Rise/Fall Time
F_SEL[1:0] 00 46 odc Output Duty Cycle F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.67 170 113.33 56.67 12 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 0.78 0.67 0.69 0.82 0.75 200 700 54 58 Units MHz MHz MH z MH z ps ps ps ps ps ps ps % %
TABLE 6C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 3
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF odc
Output Rise/Fall Time Output Duty Cycle
F_SEL[1:0] 00 46 F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
0 -10 -20 -30 -40 -50
Fibre Channel Filter 53.125MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 0.68ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE AT 212.5MHZ @3.3V
0 -10 -20 -30 -40 -50
Fibre Channel Filter 212.5MHz
RMS Phase Jitter (Random) 637KHz to 10MHz = 0.83ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -160 -170 -180 -190 100 1k 10k 100k
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel to raw data
1M 10M 100M
-150
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA
SCOPE
VDDO GND
Qx
LVCMOS
GND
LVCMOS
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDD, VDDA, VDDO
SCOPE
Qx
Noise Power
Phase Noise Mask
LVCMOS
GND
f1
Offset Frequency
f2
-1.25V5%
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDO
RMS PHASE JITTER
80% 20% tR tF 80% 20%
Qx
2
V
DDO
Clock Outputs
Qy
2 tsk(o)
OUTPUT SKEW
V
DDO
OUTPUT RISE/FALL TIME
Q0, Q1
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840002I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS840002I
Figure 2. CRYSTAL INPUt INTERFACE
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins.
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840002I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install VDD
R2 33
Zo = 50 Ohm
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
U1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Zo = 50 Ohm C5 0.1u XTAL2 R4 100
LVCMOS
VDD R1 10
VDDA C3 10uF C4 0.01u C6 0.1u
FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD
FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT
VDD R3 100
ICS840002I
If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground.
LVCMOS C2 22pF X1 XTAL1
Optional Termination
C1 22pF
Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated.
FIGURE 3. ICS840002I SCHEMATIC EXAMPLE
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
137.1C/W 89.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840002I is: 3085
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ICS840002I
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
16 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS840002AGI ICS840002AGIT ICS840002AGILF ICS840002AGILFT Marking ICS840002AI ICS840002AI TBD TBD Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging 94 per tube 2500 94 per tube 2500 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM
are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AGI www.icst.com/products/hiperclocks.html REV. A MARCH 10, 2005
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